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Analyzing SEU Effects in SRAM-based FPGAs
Kos Island, Greece July 07-July 09
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/OLT.2003.12143779th IEEE International On-Line Testin ...
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M. Violante, Politecnico di Torino
M. Ceschia, Universit? di Padova; Istituto Nazionale di Fisica Nucleare
M. Sonza Reorda, Politecnico di Torino
A. Paccagnella, Universit? di Padova; Istituto Nazionale di Fisica Nucleare
P. Bernardi, Politecnico di Torino
M. Rebaudengo, Politecnico di Torino
D. Bortolato, Universit? di Padova
M. Bellato, Istituto Nazionale di Fisica Nucleare
P. Zambolin, Universit? di Padova
A. Candelori, Istituto Nazionale di Fisica Nucleare
Commercial-Off-The-Shelf SRAM-based FPGA devices are becoming of interests for applications where high dependability and low cost are mandatory constraints. This paper proposes a new method for assessing the effects of SEUs in the device configuration memory. The method combines radiation testing for technology characterization and simulation-based fault injection for SEU propagation. Experimental results we gathered with the purpose of modeling the effects of SEUs in the FPGA configuration memory are reported and commented.
Citation:
M. Violante, M. Ceschia, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori, "Analyzing SEU Effects in SRAM-based FPGAs," iolts, pp.119, 9th IEEE International On-Line Testing Symposium, 2003
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