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Testing FPGA Delay Faults in the System Environment is Very Different from "Ordinary" Delay Fault Testing
Taormina, Italy July 09-July 11
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/OLT.2001.937815Seventh International On-Line Testing ...
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Andrzej Krasniewski, Warsaw University of Technology
Abstract: We explain differences between testing delay faults in FPGAs and testing delay faults in circuits whose combinational sections can be represented as gate networks. We formulate - in a form suitable for analysis of LUT-based FPGAs - conditions that allow one to check whether or not a given input pair is a test of specific type (non-robust, robust, etc.). The presented theoretical results are shown to simplify an analysis of the various methods for enhancing the effectiveness of detection of FPGA delay faults.
Citation:
Andrzej Krasniewski, "Testing FPGA Delay Faults in the System Environment is Very Different from "Ordinary" Delay Fault Testing," ioltw, pp.0037, Seventh International On-Line Testing Workshop, 2001
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