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Automatic Insertion of Fault-Tolerant Structures at the RT Level
Taormina, Italy July 09-July 11
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/OLT.2001.937817Seventh International On-Line Testing ...
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Luis Entrena, Universidad Carlos III de Madrid
Celia López, Universidad Carlos III de Madrid
Emilio Olías, Universidad Carlos III de Madrid
Abstract: Historically, there has been a lack of CAD tools for the design of on-line testable circuits. As a consequence, the design of on-line testable circuits is currently being made manually to a large extent. In this paper we propose a new tool for the automatic insertion of fault-tolerant structures in an HDL synthesizable description of the design. With this tool, a fault-tolerant version of the design can be automatically produced according to the user specifications. The resulting fault-tolerant design is also described in an HDL and can be simulated and synthesized with commercial tools. Examples are shown to demonstrate the capabilities of this approach.
Citation:
Luis Entrena, Celia López, Emilio Olías, "Automatic Insertion of Fault-Tolerant Structures at the RT Level," ioltw, pp.0048, Seventh International On-Line Testing Workshop, 2001
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