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On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity
Taormina, Italy July 09-July 11
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/OLT.2001.937818Seventh International On-Line Testing ...
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M. Pflanz, BTU Cottbus
K. Walther, BTU Cottbus
H.T. Vierhaus, BTU Cottbus
Abstract: This paper presents efficient techniques for concurrent error detection of processor components. It deals with concurrent check methods for complex data-path elements like FPUs or register-files. We propose a Berger code prediction unit for a multistage add-sub-FPU. Furthermore, the suitability of Berger code for register-files is discussed. As an alternative, the Cross-Parity observation is introduced. The applicability of these concepts was evaluated on several experimental processor designs up to double-precision pipeline processors.
Citation:
M. Pflanz, K. Walther, H.T. Vierhaus, "On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity," ioltw, pp.0051, Seventh International On-Line Testing Workshop, 2001
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