A Gated Clock Scheme for Low Power Scan-Based BIST

Taormina, Italy July 09-July 11

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http://doi.ieeecomputersociety.org/10.1109/OLT.2001.937824

Seventh International On-Line Testing ...

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	ASCII Text	x
	Y. Bonhomme P. Girard L. Guiller C. Landrault, S. Pravossoudovitch, "A Gated Clock Scheme for Low Power Scan-Based BIST," On-Line Testing Workshop, IEEE International, pp. 0087, Seventh International On-Line Testing Workshop, 2001.

	BibTex	x
	@article{ 10.1109/OLT.2001.937824, author = {Y. Bonhomme P. Girard L. Guiller C. Landrault and S. Pravossoudovitch}, title = {A Gated Clock Scheme for Low Power Scan-Based BIST}, journal ={On-Line Testing Workshop, IEEE International}, volume = {0}, year = {2001}, isbn = {0-7695-1290-9}, pages = {0087}, doi = {http://doi.ieeecomputersociety.org/10.1109/OLT.2001.937824}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - On-Line Testing Workshop, IEEE International TI - A Gated Clock Scheme for Low Power Scan-Based BIST SN - 0-7695-1290-9 SP EP A1 - Y. Bonhomme P. Girard L. Guiller C. Landrault, A1 - S. Pravossoudovitch, PY - 2001 VL - 0 JA - On-Line Testing Workshop, IEEE International ER -

Y. Bonhomme P. Girard L. Guiller C. Landrault, Universit? Montpellier II

S. Pravossoudovitch, Universit? Montpellier II

Abstract: In this paper, we present a new low power scan-based BIST technique which can reduce the switching activity during test operation. The proposed low power/energy technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path.

Citation:

Y. Bonhomme P. Girard L. Guiller C. Landrault, S. Pravossoudovitch, "A Gated Clock Scheme for Low Power Scan-Based BIST," ioltw, pp.0087, Seventh International On-Line Testing Workshop, 2001

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