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Multi-Level Fault Injection Experiments Based on VHDL Descriptions: A Case Study
Isle of Bendor, France July 08-July 10
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/OLT.2002.1030192Proceedings of The Eighth IEEE Intern ...
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R. Leveugle, TIMA Laboratory
K. Hadjiat, TIMA Laboratory
The probability of transient faults increases with the evolution of technologies. There is a corresponding increased demand for an early analysis of erroneous behaviors. This paper reports on results obtained with SEU-like fault injections in VHDL descriptions of digital circuits. Several circuit description levels are considered, as well as several fault modeling levels. These results show that an analysis performed at a very early stage in the design process can actually give a helpful insight into the response of a circuit when a fault occurs.
Index Terms:
VLSI design, VHDL, fault injection, dependability analysis
Citation:
R. Leveugle, K. Hadjiat, "Multi-Level Fault Injection Experiments Based on VHDL Descriptions: A Case Study," ioltw, pp.107, Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02), 2002
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