A BIST method enabling two-pattern testing at-speed without violating thermal constraints by introducing cool down periods is proposed. The application of the method is demonstrated based on a scalable BIST architecture. Applicability on IP cores is given since only a two-pattern test set is required as input.
Index Terms:
BIST, Thermal constraints, Delay testing, IP cores
Citation:
Ilia Polian, Bernd Becker, "Stop & Go BIST," ioltw, pp.147, Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02), 2002