loading...
On-line Detection and Compensation of Transient Errors in Processor Pipeline-Structures
Isle of Bendor, France July 08-July 10
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/OLT.2002.1030204Proceedings of The Eighth IEEE Intern ...
 This Article 
 
PURCHASE ARTICLE: $0
HTML
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
C. Galke, Brandenburg University of Technology Cottbus
M. Pflanz, IBM Deutschland Entwicklung GmbH
H. T. Vierhaus, Brandenburg University of Technology Cottbus
Based on strategies for on-line error detection in data and control path structures in simple microprocessors, this approach proposes techniques for the control- and component-error detection in high-performance processors. Detected errors are classified on-line with respect to their impact on the control and data flow. A compensation of detected errors is performed by micro rollback with different rollback distances according to predefined priority classes of error handling.
Citation:
C. Galke, M. Pflanz, H. T. Vierhaus, "On-line Detection and Compensation of Transient Errors in Processor Pipeline-Structures," ioltw, pp.178, Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02), 2002
Usage of this product signifies your acceptance of the Terms of Use.