Recovering Sequential Circuits from Temporary Faults: The Survival Capability of Scan-Cells

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http://doi.ieeecomputersociety.org/10.1109/OLT.2002.1030205

Proceedings of The Eighth IEEE Intern ...

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	Jose Miguel Vieira dos Santos, "Recovering Sequential Circuits from Temporary Faults: The Survival Capability of Scan-Cells," On-Line Testing Workshop, IEEE International, pp. 179, Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02), 2002.

	BibTex	x
	@article{ 10.1109/OLT.2002.1030205, author = {Jose Miguel Vieira dos Santos}, title = {Recovering Sequential Circuits from Temporary Faults: The Survival Capability of Scan-Cells}, journal ={On-Line Testing Workshop, IEEE International}, volume = {0}, year = {2002}, isbn = {0-7695-1641-6}, pages = {179}, doi = {http://doi.ieeecomputersociety.org/10.1109/OLT.2002.1030205}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - On-Line Testing Workshop, IEEE International TI - Recovering Sequential Circuits from Temporary Faults: The Survival Capability of Scan-Cells SN - 0-7695-1641-6 SP EP A1 - Jose Miguel Vieira dos Santos, PY - 2002 KW - Dependability KW - DFT KW - Sequential logic KW - BST VL - 0 JA - On-Line Testing Workshop, IEEE International ER -

Jose Miguel Vieira dos Santos, ISEP - DEE

The recovery technique introduced in this paper can be implemented in new designs and may allow sequential circuits to recover from many temporary faults. It is assumed that errors will be detected by other means. The memory elements of the mission circuit are implemented with standard, slightly enhanced, scan-cells that work as stand-alone, needing no external control or support.

Index Terms:

Dependability, DFT, Sequential logic, BST

Citation:

Jose Miguel Vieira dos Santos, "Recovering Sequential Circuits from Temporary Faults: The Survival Capability of Scan-Cells," ioltw, pp.179, Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02), 2002

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