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A Single-Chip Supervised Partial Self-Reconfigurable Architecture for Software Defined Radio
Nice, France April 22-April 26
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IPDPS.2003.1213354International Parallel and Distribute ...
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Oliver Faust, Ngee Ann Polytechnic
Bernhard Sputh, Ngee Ann Polytechnic
Darran Nathan, Ngee Ann Polytechnic
Sana Rezgui, Ngee Ann Polytechnic
Andreas Weisensee, Ngee Ann Polytechnic
Alastair Allen, University of Aberdeen
Software Defined Radio (SDR) technology seeks to solve the problem of multiple incompatible broadcast/telecom standards available in different locations, by having standard specific processing defined in software. This software will be downloaded and run on generic hardware, so that different broadcast/telecom standards can be supported by downloading corresponding software modules. Computing platform based SDR attempts to bridge the worlds of computing and broadcast/telecoms, by exposing the features and resources of computers to SDR and vice versa. However, such a concept results in certain architectural issues that need to be resolved. This paper describes the concept of Computing Platform based SDR, and the resulting issues & desired features of such a system. An innovative system architecture that involves the supervised partial self-reconfiguration of a single FPGA is proposed and detailed. Finally, a system test is conducted to illustrate and verify the reconfiguration operation.
Citation:
Oliver Faust, Bernhard Sputh, Darran Nathan, Sana Rezgui, Andreas Weisensee, Alastair Allen, "A Single-Chip Supervised Partial Self-Reconfigurable Architecture for Software Defined Radio," ipdps, pp.191a, International Parallel and Distributed Processing Symposium (IPDPS'03), 2003
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