Z. Vranesic,
"The FPGA Challenge,"
Multiple-Valued Logic, IEEE International Symposium on, pp. 121, The 28th International Symposium on Multiple-Valued Logic, 1998.
BibTex
x
@article{
10.1109/ISMVL.1998.679318, author = {Z. Vranesic}, title = {The FPGA Challenge}, journal ={Multiple-Valued Logic, IEEE International Symposium on}, volume = {0}, year = {1998}, issn = {0195-623X}, pages = {121}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISMVL.1998.679318}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
x
TY - CONF JO - Multiple-Valued Logic, IEEE International Symposium on TI - The FPGA Challenge SN - 0195-623X SP EP A1 - Z. Vranesic, PY - 1998 VL - 0 JA - Multiple-Valued Logic, IEEE International Symposium on ER -
PURCHASE ARTICLE: $19
IEEE Xplore Subscribers
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb