T. Aoki, T. Higuchi,
"Set-Valued Logic Circuits for Next Generation VLSI Architectures,"
Multiple-Valued Logic, IEEE International Symposium on, pp. 140, The 28th International Symposium on Multiple-Valued Logic, 1998.
BibTex
x
@article{
10.1109/ISMVL.1998.679324, author = {T. Aoki and T. Higuchi}, title = {Set-Valued Logic Circuits for Next Generation VLSI Architectures}, journal ={Multiple-Valued Logic, IEEE International Symposium on}, volume = {0}, year = {1998}, issn = {0195-623X}, pages = {140}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISMVL.1998.679324}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
x
TY - CONF JO - Multiple-Valued Logic, IEEE International Symposium on TI - Set-Valued Logic Circuits for Next Generation VLSI Architectures SN - 0195-623X SP EP A1 - T. Aoki, A1 - T. Higuchi, PY - 1998 VL - 0 JA - Multiple-Valued Logic, IEEE International Symposium on ER -
T. Aoki, T. Higuchi, "Set-Valued Logic Circuits for Next Generation VLSI Architectures," ismvl, pp.140, The 28th International Symposium on Multiple-Valued Logic, 1998
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