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A Novel D-Latch in Multiple-Valued Semi-Floating-Gate Recharged Logic
University of Toronto, Toronto, Canada May 19-May 22
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.2004.131994334th International Symposium on Multi ...
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Omid Mirmotahari, Yngvar Berg, "A Novel D-Latch in Multiple-Valued Semi-Floating-Gate Recharged Logic," Multiple-Valued Logic, IEEE International Symposium on, pp. 210-213, 34th International Symposium on Multiple-Valued Logic (ISMVL'04), 2004.
 
 
BibTex
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@article{ 10.1109/ISMVL.2004.1319943,
author = {Omid Mirmotahari and Yngvar Berg},
title = {A Novel D-Latch in Multiple-Valued Semi-Floating-Gate Recharged Logic},
journal ={Multiple-Valued Logic, IEEE International Symposium on},
volume = {0},
year = {2004},
issn = {0195-623X},
pages = {210-213},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISMVL.2004.1319943},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Multiple-Valued Logic, IEEE International Symposium on
TI - A Novel D-Latch in Multiple-Valued Semi-Floating-Gate Recharged Logic
SN - 0195-623X
SP210
EP213
A1 - Omid Mirmotahari,
A1 - Yngvar Berg,
PY - 2004
KW - null
VL - 0
JA - Multiple-Valued Logic, IEEE International Symposium on
ER -
 
Omid Mirmotahari, University of Oslo
Yngvar Berg, University of Oslo
In this paper we present several different proposals for implementing a multiple-valued (MV) semi-floating-gate (SFG) D-latch. This paper aims to illustrate the advantages and disadvantages of each approach. Measurements from a fabricated chip at a 0.6?m CUP process is included for verifying the detailed arguments.
Citation:
Omid Mirmotahari, Yngvar Berg, "A Novel D-Latch in Multiple-Valued Semi-Floating-Gate Recharged Logic," ismvl, pp.210-213, 34th International Symposium on Multiple-Valued Logic (ISMVL'04), 2004
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