As VLSI technology has developed, the interest in implementing an entire or significant part of a parallel computer system using wafer scale integration is growing. The major problem for the case is the possibility of drastically low yield and/or reliability of the system if there is no strategy for coping with such situations.In this paper, we propose a reconfigurable processor array based on the 1 1/2-track switch model (shortly denoted as 1 1/2-TS model) such that spare PEs are not necessarily put around the array, but are more flexibly put in the array by changing connections of spare PEs to nonspare PEs while retaining the connections among nonspare PEs in the same manner as those in 1 1/2-TS model.The proposed model has such a desirable property that physical distances between logically adjacent PEs in the reconfigured array are within a constant, that is, independent of sizes of arrays. We show that the hardware overhead of the proposed model is a little greater than that of 1 1/2-TS model, while the yield of the proposed model is much better than that of 1 1/2-TS model.