Power supply noise can significantly impact the performance of deep submicron designs. Existing timing analysis techniques cannot capture the effects of power supply noise on the signal/cell delays. This is because these delay effects are highly input pattern dependent. Therefore, the predicted circuit performance might not reflect the worst-case circuit delay. In this paper, we propose a dynamic timing analysis technique that can take into account the impact of the power supply noise on the signal/cell propagation delays. Our technique is based on considering the input patterns that produce the worst-case power supply noise effects on the propagation delays of the longest true paths in the circuit. Our experimental results show that the circuit delay predicted by our dynamic timing analysis method is significantly longer than the delay predicted using traditional timing analysis tools.