Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process

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http://doi.ieeecomputersociety.org/10.1109/ISQED.2001.915241

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	Ming-Dou Ker, Wen-Yu Lo, Tung-Yang Chen, Howard Tang, S.-S. Chen, M.-C. Wang, "Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process," Quality Electronic Design, International Symposium on, pp. 267, International Symposium on Quality Electronic Design (ISQED '01), 2001.

	BibTex	x
	@article{ 10.1109/ISQED.2001.915241, author = {Ming-Dou Ker and Wen-Yu Lo and Tung-Yang Chen and Howard Tang and S.-S. Chen and M.-C. Wang}, title = {Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2001}, isbn = {0-7695-1025-6}, pages = {267}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2001.915241}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process SN - 0-7695-1025-6 SP EP A1 - Ming-Dou Ker, A1 - Wen-Yu Lo, A1 - Tung-Yang Chen, A1 - Howard Tang, A1 - S.-S. Chen, A1 - M.-C. Wang, PY - 2001 VL - 0 JA - Quality Electronic Design, International Symposium on ER -

Ming-Dou Ker, National Chiao-Tung University,

Wen-Yu Lo, National Chiao-Tung University,

Tung-Yang Chen, National Chiao-Tung University,

Howard Tang, United Microelectronics Corporation (UMC)

S.-S. Chen, United Microelectronics Corporation (UMC)

M.-C. Wang, United Microelectronics Corporation (UMC)

An experimental extraction to find the area-efficient compact layout rules to prevent latchup in bulk CMOS IC's is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances. A new efficient latchup prevention design, by adding the additional internal guard rings between the I/O cells and the internal core circuits, has been successfully proven in a 0.25-mm shallow-trench-isolation (STI) silicided bulk CMOS process. Through detailed experimental verification including temperature effect, the proposed extraction method to define compact layout rules has been established to save the silicon area of CMOS IC's, but still to maintain high enough latchup immunity in bulk CMOS IC's.

Citation:

Ming-Dou Ker, Wen-Yu Lo, Tung-Yang Chen, Howard Tang, S.-S. Chen, M.-C. Wang, "Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process," isqed, pp.267, International Symposium on Quality Electronic Design (ISQED '01), 2001

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