Leakage performance of BCPMOS (Buried Channel PMOS) is investigated by experimentally varying the LDD implant conditions. An anomalous leakage increase with Boron LDD implant is observed for a small geometry (narrow and short) PMOS. Experimental results indicate that the increase of leakage current for narrow and short channel PMOS can be explained by boron piling up at the edge of STI isolation and from source/drain towards the middle of channel. Further con.rmation of boron piling up is proven by the surface channel NMOS threshold voltage. Based on the leakage sensitivity, BC PMOS LDD is optimized to reduce leakage current for the small geometry transistors.