The subthreshold leakage current characteristics of domino logic circuits is evaluated in this paper. The strong dependence of the subthreshold leakage current on the node voltages is discussed. In a standard low threshold voltage domino logic circuit with stacked pull-down devices, a charged state rather than a discharge state of the dynamic node is preferred for lower leakage current. Alternatively, the subthreshold leakage current of a dual threshold voltage domino logic circuit is significantly reduced provided that the dynamic node is discharged.

A dual threshold voltage circuit has degraded noise immunity characteristics as compared to a standard low threshold voltage circuit. Both keeper and output inverter sizing are necessary to compensate for this degradation in noise immunity. An alternative dual threshold voltage domino circuit technique employing a low threshold voltage keeper for enhanced noise immunity is also considered in this paper. Under similar noise immunity conditions as compared to a standard low threshold voltage domino logic circuit, the savings in subthreshold leakage current offered by a dual threshold voltage circuit technique with a high threshold voltage keeper is significantly higher than the savings offered by a dual threshold voltage circuit technique with a low threshold voltage keeper.