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Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD)
San Jose, California March 22-March 24
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2004.12836595th International Symposium on Qualit ...
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Youngsik Kim, Shekhar Kopuri, Nazanin Mansouri, "Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD)," Quality Electronic Design, International Symposium on, pp. 110-115, 5th International Symposium on Quality Electronic Design (ISQED'04), 2004.
 
 
BibTex
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@article{ 10.1109/ISQED.2004.1283659,
author = {Youngsik Kim and Shekhar Kopuri and Nazanin Mansouri},
title = {Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD)},
journal ={Quality Electronic Design, International Symposium on},
volume = {0},
year = {2004},
issn = {2003116307},
pages = {110-115},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2004.1283659},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Quality Electronic Design, International Symposium on
TI - Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD)
SN - 2003116307
SP110
EP115
A1 - Youngsik Kim,
A1 - Shekhar Kopuri,
A1 - Nazanin Mansouri,
PY - 2004
KW - null
VL - 0
JA - Quality Electronic Design, International Symposium on
ER -
 
Youngsik Kim, Syracuse University
Shekhar Kopuri, Syracuse University
Nazanin Mansouri, Syracuse University
This paper presents a methodology for the formal verification of scheduling during High-Level Synthesis(HLS). A notion of functional equivalence between two Finite State Machines with Datapath (FSMDs) is de.ned, on the basis of which we propose a methodology to verify scheduling. The functional equivalence between the behavioral specification and the scheduled Control-Data Flow Graph (CDFG) - that is the result of scheduling - is established using their FSMD models. The equivalence conditions are mathematically modeled and implemented in the higher-order specification language of theorem proving environment PVS [11], integrated with a HLS tool. The proof of correctness of the design is subsequently verified by the PVS proof checker.
Citation:
Youngsik Kim, Shekhar Kopuri, Nazanin Mansouri, "Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD)," isqed, pp.110-115, 5th International Symposium on Quality Electronic Design (ISQED'04), 2004
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