This paper proposes an exact cell layout synthesis technique to minimize the probability of wiring faults due to spot defects. We modeled the probability of faults on intra-cell routings with considering the spot defects size distribution and the end effect of critical areas. By using the model as a cost function, we comprehensively generate the minimum width layout of CMOS logic cells and select the optimum layouts. Experimental results show that our technique reduces about 15% of the fault probabilities compared with the wire-length-minimum layouts for CMOS logic circuits which have up to 14 transistors.