Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design

Kyoto, Japan October 02-October 04

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http://doi.ieeecomputersociety.org/10.1109/ISSS.2002.1227147

Proceedings of the 15th international ...

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	Ahmed A. Jerraya, Damien Lyonnard, Samy Meftali, Fr?d?ric Rousseau, F?rid Gharsalli, "Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design," System Synthesis, International Symposium on, pp. 26-31, Proceedings of the 15th international symposium on System Synthesis (ISSS '02), 2002.

	BibTex	x
	@article{ 10.1109/ISSS.2002.1227147, author = {Ahmed A. Jerraya and Damien Lyonnard and Samy Meftali and Fr?d?ric Rousseau and F?rid Gharsalli}, title = {Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design}, journal ={System Synthesis, International Symposium on}, volume = {0}, year = {2002}, isbn = {1-58113-576-9}, pages = {26-31}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISSS.2002.1227147}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - System Synthesis, International Symposium on TI - Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design SN - 1-58113-576-9 SP26 EP31 A1 - Ahmed A. Jerraya, A1 - Damien Lyonnard, A1 - Samy Meftali, A1 - Fr?d?ric Rousseau, A1 - F?rid Gharsalli, PY - 2002 KW - embedded memory KW - memory access KW - memory wrapper generation KW - system-on-chip VL - 0 JA - System Synthesis, International Symposium on ER -

Ahmed A. Jerraya, Laboratoire TIMA, Grenoble cedex, France

Damien Lyonnard, Laboratoire TIMA, Grenoble cedex, France

Samy Meftali, Laboratoire TIMA, Grenoble cedex, France

Fr?d?ric Rousseau, Laboratoire TIMA, Grenoble cedex, France

F?rid Gharsalli, Laboratoire TIMA, Grenoble cedex, France

In this paper, we present a new methodology for application specific multiprocessor system-on-chip design. This approach facilitates the integration of existing components with the concept of wrapper. Wrappers allow automatic adaptation of physical interfaces to a communication network. We also give a generic architecture to produce these wrappers, either for processors or for other specific components such as memory IP. This approach has successfully been applied on a low-level image processing application.

Index Terms:

embedded memory, memory access, memory wrapper generation, system-on-chip

Citation:

Ahmed A. Jerraya, Damien Lyonnard, Samy Meftali, Fr?d?ric Rousseau, F?rid Gharsalli, "Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design," isss, pp.26-31, Proceedings of the 15th international symposium on System Synthesis (ISSS '02), 2002

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