Energy/Power Estimation of Regular Processor Arrays

Kyoto, Japan October 02-October 04

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/ISSS.2002.1227151

Proceedings of the 15th international ...

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Sanjay Rajopadhye Articles by Steven Derrien

	ASCII Text	x
	Sanjay Rajopadhye, Steven Derrien, "Energy/Power Estimation of Regular Processor Arrays," System Synthesis, International Symposium on, pp. 50-55, Proceedings of the 15th international symposium on System Synthesis (ISSS '02), 2002.

	BibTex	x
	@article{ 10.1109/ISSS.2002.1227151, author = {Sanjay Rajopadhye and Steven Derrien}, title = {Energy/Power Estimation of Regular Processor Arrays}, journal ={System Synthesis, International Symposium on}, volume = {0}, year = {2002}, isbn = {1-58113-576-9}, pages = {50-55}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISSS.2002.1227151}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - System Synthesis, International Symposium on TI - Energy/Power Estimation of Regular Processor Arrays SN - 1-58113-576-9 SP50 EP55 A1 - Sanjay Rajopadhye, A1 - Steven Derrien, PY - 2002 KW - design space exploration KW - power estimation KW - processor array partitioning KW - programmable logic VL - 0 JA - System Synthesis, International Symposium on ER -

Sanjay Rajopadhye, Colorado State University

Steven Derrien, IRISA, France

We propose a high-level analytical model for estimating the energy and/or power dissipation in VLSI processor (systolic) array implementations of loop programs, particularly for implementations on FPGA based CO-processors. We focus on the respective impact of the array design parameters on the overall off-chip i/o traffic and the number and sizes of the local memories in the array. The model is validated experimentally and shows good results (12.7% RMS error in the predictions).

Index Terms:

design space exploration, power estimation, processor array partitioning, programmable logic

Citation:

Sanjay Rajopadhye, Steven Derrien, "Energy/Power Estimation of Regular Processor Arrays," isss, pp.50-55, Proceedings of the 15th international symposium on System Synthesis (ISSS '02), 2002

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.