Multi-Output Timed Shannon Circuits

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http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2002.1016873

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	Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller, "Multi-Output Timed Shannon Circuits," VLSI, IEEE Computer Society Annual Symposium on, pp. 0047, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'02), 2002.

	BibTex	x
	@article{ 10.1109/ISVLSI.2002.1016873, author = {Mitchell A. Thornton and Rolf Drechsler and D. Michael Miller}, title = {Multi-Output Timed Shannon Circuits}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2002}, isbn = {0-7695-1486-3}, pages = {0047}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2002.1016873}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Multi-Output Timed Shannon Circuits SN - 0-7695-1486-3 SP EP A1 - Mitchell A. Thornton, A1 - Rolf Drechsler, A1 - D. Michael Miller, PY - 2002 KW - Logic Synthesis KW - Low Power KW - BDD VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Mitchell A. Thornton, Mississippi State University

Rolf Drechsler, University of Bremen

D. Michael Miller, University of Victoria

Timed Shannon circuits have been proposed as a synthesis approach for a low power optimization technique at the logic level since overall circuit switching probabilities may be reduced. An improvement in the application of this principle for multi-output circuits is presented. Techniques that trade area for power reduction and a method for minimizing the overall circuit switching probability are also included. Experimental results are given and analyzed for these techniques.

Index Terms:

Logic Synthesis, Low Power, BDD

Citation:

Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller, "Multi-Output Timed Shannon Circuits," isvlsi, pp.0047, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'02), 2002

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