Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS

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http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2003.1183350

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	Koushik K. Das, Richard B. Brown, "Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS," VLSI, IEEE Computer Society Annual Symposium on, pp. 29, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03), 2003.

	BibTex	x
	@article{ 10.1109/ISVLSI.2003.1183350, author = {Koushik K. Das and Richard B. Brown}, title = {Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2003}, isbn = {0-7695-1904-0}, pages = {29}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2003.1183350}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS SN - 0-7695-1904-0 SP EP A1 - Koushik K. Das, A1 - Richard B. Brown, PY - 2003 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Koushik K. Das, University of Michigan

Richard B. Brown, University of Michigan

SOI (silicon-on-insulator)technology suffers from a number of floating body effects,most notably parasitic bipolar and history effects.These are influenced by the rapidly increasing gate tunneling current caused by an ultra-thin gate oxide,even at scaled V_Ds [8 ].This paper analyzes these effects in detail and proposes a number of novel circuit styles to minimize them.Simulation results are based on model parameters from an AMD 0.25 ?m PD-SOI process.

Citation:

Koushik K. Das, Richard B. Brown, "Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS," isvlsi, pp.29, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03), 2003

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