loading...
Optimal shielding/spacing metrics for low power design
Tampa, Florida February 20-February 21
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2003.1183442IEEE Computer Society Annual Symposiu ...
 This Article 
 
PDF
HTML
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Ravishankar Arunachalam, I.B.M Electronic Design Automation
Emrah Acar, I.B.M Austin Research Lab
Sani R. Nassif, I.B.M Austin Research Lab
Noise arising from line-to-line coupling is a major problem for deep submicron design, and present technology trends are causing an increase in this type of noise. Common current methods to decrease coupling noise include shielding and buffering, both of which can increase overall power dissipation. An alternative method is spacing, which has the added benefit of improving the manufacturability (i.e.defect insensitivity) of the design. This paper explores the issue of coupling noise reduction, and proposes performance metrics that can be used by the designer to determine which of the alternative methods is best suited for a specific interconnect configuration.
Citation:
Ravishankar Arunachalam, Emrah Acar, Sani R. Nassif, "Optimal shielding/spacing metrics for low power design," isvlsi, pp.167, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03), 2003
Usage of this product signifies your acceptance of the Terms of Use.