In ultra deep submicron (UDSM) circuit design, the interconnect delay and noise have become the dominant factors in determining circuit performance. Analytical expressions are preferred because simulation is always expensive and ineffective in use with modern designs containing millions of transistors and wires. However, analytical expressions are not sufficiently accurate and do not consider all of interconnect and driver parameters. In this paper, we analyze the effects of all known interconnect and driver parameters on the crosstalk peak noise, crosstalk noise pulse width, and the impact of coupling on aggressor delay. We consider parameters like spacing between wires, wire length, coupling length, load capacitance, rise time of the inputs, place of overlap (near driver or receiver side), frequency, direction of the signals, wire width for both the aggressors and the victim wires. Also, we consider parameters like driver strength as several recent studies considered the simultaneous device and interconnect sizing.