It is envisioned that future system-on-chip hardware platform designs will be based on reuse of a customizable processor core. Consequently, being able to quickly evaluate the key performance metrics associated with specific points in the design space becomes essential. Development of an early design phase performance estimation method for logic blocks of an extensible processor core is described. The processor blocks were systematically synthesized with varying constraints for reference and the corresponding Rent?s exponents were extracted from the results. The impact of synthesis- originated design space discontinuities on the accuracy of physical performance estimation was evaluated by applying linear regression on the resulting design points.