Nosie issues in deep sub-micron CMOS VLSI circuits have an importance comparable to area, delay and power consumption issues due to aggressive scaling trends in devices and interconnections. An attempt has been made to address this problem in this paper. A new technique to make dynamic CMOS circuits noise tolerant has been proposed in this paper. Simulation results for a dynamic- CMOS NAND gate and a dynamic-CMOS 1-Bit full-adder circuit show that the propsed technique has an improvement in ANTE of 6.0X over conventional dynamic logic. The proposed technique, in comparison with the twin transistor technique, proves to improve ANTE by 2.8X. There is a large power dissipation incurred during the evaluation period for certain input combinations.