Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects

Tampa, Florida February 20-February 21

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2003.1183477

IEEE Computer Society Annual Symposiu ...

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Per Larsson-Edefors Articles by Daniel Eckerbert Articles by Henrik Eriksson Articles by Lars "J" Svensson

	ASCII Text	x
	Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson, Lars "J" Svensson, "Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects," VLSI, IEEE Computer Society Annual Symposium on, pp. 225, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03), 2003.

	BibTex	x
	@article{ 10.1109/ISVLSI.2003.1183477, author = {Per Larsson-Edefors and Daniel Eckerbert and Henrik Eriksson and Lars "J" Svensson}, title = {Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2003}, isbn = {0-7695-1904-0}, pages = {225}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2003.1183477}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects SN - 0-7695-1904-0 SP EP A1 - Per Larsson-Edefors, A1 - Daniel Eckerbert, A1 - Henrik Eriksson, A1 - Lars "J" Svensson, PY - 2003 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Per Larsson-Edefors, Chalmers University of Technology

Daniel Eckerbert, Chalmers University of Technology

Henrik Eriksson, Chalmers University of Technology

Lars "J" Svensson, Chalmers University of Technology

We consider the power-optimal design of dual-V_T CMOS circuits under challenging delay constraints, with threshold voltages and device sizes as design variables. We show that the presence of interconnect resistance affects the optimum choices of V_T and device sizes, and that ignoring the resistance can lead to highly suboptimal results. We also present criteria for deciding when interconnect resistance should be taken into account.

Citation:

Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson, Lars "J" Svensson, "Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects," isvlsi, pp.225, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03), 2003

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.