Earl E. Swartzlander, Jr.,
"A Review of Large Parallel Counter Designs,"
VLSI, IEEE Computer Society Annual Symposium on, pp. 89, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004.
BibTex
x
@article{
10.1109/ISVLSI.2004.1339513, author = {Earl E. Swartzlander, Jr.}, title = {A Review of Large Parallel Counter Designs}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2004}, isbn = {0-7695-2097-9}, pages = {89}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339513}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
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TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - A Review of Large Parallel Counter Designs SN - 0-7695-2097-9 SP EP A1 - Earl E. Swartzlander, Jr., PY - 2004 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -
Parallel counters are key elements of many arithmetic elements, especially fast multipliers. This paper reviews a number of counter designs that have been presented over the last four decades. In this paper, the emphasis is on (7, 3) counters.
Citation:
Earl E. Swartzlander, Jr., "A Review of Large Parallel Counter Designs," isvlsi, pp.89, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004
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