Low Power 2.5 Gb/s Serializer for SOC Applications

Lafayette, Louisiana February 19-February 20

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http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339532

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	K. Iniewski, M. Syrzycki, "Low Power 2.5 Gb/s Serializer for SOC Applications," VLSI, IEEE Computer Society Annual Symposium on, pp. 211, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004.

	BibTex	x
	@article{ 10.1109/ISVLSI.2004.1339532, author = {K. Iniewski and M. Syrzycki}, title = {Low Power 2.5 Gb/s Serializer for SOC Applications}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2004}, isbn = {0-7695-2097-9}, pages = {211}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339532}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Low Power 2.5 Gb/s Serializer for SOC Applications SN - 0-7695-2097-9 SP EP A1 - K. Iniewski, A1 - M. Syrzycki, PY - 2004 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

K. Iniewski, Simon Fraser University

M. Syrzycki, Simon Fraser University

2.5 Gb/s serializer suitable for System-On-the-Chip (SOC) implementation is presented. Phase Lock Loop architecture is of Type IV that results in superior performance for Power Supply Rejection Ratio (PSRR). The circuit has been implemented in 0.18 mm standard CMOS process, occupies 1230 mm by 248 mm and dissipates 128mW. The serializer has been designed for OC-48 SONET/SDH but can be used in variety of other communication and computer protocols and applications like Infiniband, RAPID I/O (RIO) and PCI Express.

Citation:

K. Iniewski, M. Syrzycki, "Low Power 2.5 Gb/s Serializer for SOC Applications," isvlsi, pp.211, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004

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