Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications

Lafayette, Louisiana February 19-February 20

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339562

IEEE Computer Society Annual Symposiu ...

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by S. Matakias Articles by Y. Tsiatouhas Articles by Th. Haniotakis Articles by A. Arapoyanni

	ASCII Text	x
	S. Matakias, Y. Tsiatouhas, Th. Haniotakis, A. Arapoyanni, "Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications," VLSI, IEEE Computer Society Annual Symposium on, pp. 293, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004.

	BibTex	x
	@article{ 10.1109/ISVLSI.2004.1339562, author = {S. Matakias and Y. Tsiatouhas and Th. Haniotakis and A. Arapoyanni}, title = {Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2004}, isbn = {0-7695-2097-9}, pages = {293}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339562}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications SN - 0-7695-2097-9 SP EP A1 - S. Matakias, A1 - Y. Tsiatouhas, A1 - Th. Haniotakis, A1 - A. Arapoyanni, PY - 2004 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

S. Matakias, University of Athens

Y. Tsiatouhas, University of Ioannina

Th. Haniotakis, Southern Illinois University

A. Arapoyanni, University of Athens

A novel current mode, periodic outputs, parallel two-rail code (TRC) checker is presented. The proposed topology is suitable for the implementation of high n-variable (high fan-in) two-rail code checkers targeting applications with a high count of monitoring lines. Compared to previous solutions the new checker is characterised by high operating frequencies and low silicon area requirements while maintaining lower power operation at higher n-variable values.

Citation:

S. Matakias, Y. Tsiatouhas, Th. Haniotakis, A. Arapoyanni, "Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications," isvlsi, pp.293, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.