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Efficient Embedded Memory Testing with APG
Baltimore, MD, USA October 07-October 10
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TEST.2002.1041744International Test Conference 2002 (I ...
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A. T. Sivaram, Daniel Fan, A. Yiin, "Efficient Embedded Memory Testing with APG," Test Conference, International, pp. 47, International Test Conference 2002 (ITC'02), 2002.
 
 
BibTex
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@article{ 10.1109/TEST.2002.1041744,
author = {A. T. Sivaram and Daniel Fan and A. Yiin},
title = {Efficient Embedded Memory Testing with APG},
journal ={Test Conference, International},
volume = {0},
year = {2002},
isbn = {0-7803-7543-2},
pages = {47},
doi = {http://doi.ieeecomputersociety.org/10.1109/TEST.2002.1041744},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Test Conference, International
TI - Efficient Embedded Memory Testing with APG
SN - 0-7803-7543-2
SP
EP
A1 - A. T. Sivaram,
A1 - Daniel Fan,
A1 - A. Yiin,
PY - 2002
KW - null
VL - 0
JA - Test Conference, International
ER -
 
A. T. Sivaram, NPTest
Daniel Fan, NPTest
A. Yiin, Intel Corporation
This paper describes the unique hardware features designed in a traditional hardware Algorithmic Pattern Generator (APG) to make full functional Direct Access Testing (DAT) of embedded memories with different data widths easier in a high volume production environment. The APG support software enables the encapsulation of pattern design for various sizes of embedded memories or arrays to significantly reduce the pattern complexity and generation effort.
Citation:
A. T. Sivaram, Daniel Fan, A. Yiin, "Efficient Embedded Memory Testing with APG," itc, pp.47, International Test Conference 2002 (ITC'02), 2002
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