To enable efficient use of debug functionality on a core-based system chip, existing core-level debug interfaces need to be re-used in one, well-defined debug architectures at chip-level. This paper describes a chip-level architecture for controlling multiple IEEE 1149.1 compliant debug interfaces on a single system chip. The presented architecture is fully compliant with the IEEE only the chip-level debug and boundary scan hardware, but also whether or not the bypass multiplexer is activated. When the chip-level TAP support are also presented to allow multiple debugger tools to control debug operations in multiple heterogeneous cores via this architecture. As an experiment, the proposed architecture is mapped on an FPGA to verify concurrent debug of multiple cores.