This paper investigates the impact of faults affecting the clock distribution network of synchronous systems on manufacturing testing. Previous researches based on real process data and Inductive Fault Analysis of a reference microprocessor showed that, contrary to common expectations, the majority of clock faults leads to local failures not likely to be detected by manufacturing testing, despite their ability to compromise the microprocessor operation and reliability. In this paper, we will show that clock faults can be detected by means of conventional stuck-at, delay and transition testing in only 12% of cases and that in 10% of cases the undetected clock faults invalidate the testing procedures themselves. In addition, in the 29% of cases, clock faults are likely to cause race conditions that, although generally not considered by delay fault testing, might as well compromise system?s correct operation. The possible adoption of on-line testing techniques to avoid such dangerous conditions will be finally discussed.