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Embedded Deterministic Test for Low-Cost Manufacturing Test
Baltimore, MD, USA October 07-October 10
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TEST.2002.1041773International Test Conference 2002 (I ...
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Januz Rajki, Jerzy Tyzer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian, "Embedded Deterministic Test for Low-Cost Manufacturing Test," Test Conference, International, pp. 301, International Test Conference 2002 (ITC'02), 2002.
 
 
BibTex
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@article{ 10.1109/TEST.2002.1041773,
author = {Januz Rajki and Jerzy Tyzer and Mark Kassab and Nilanjan Mukherjee and Rob Thompson and Kun-Han Tsai and Andre Hertwig and Nagesh Tamarapalli and Grzegorz Mrugalski and Geir Eide and Jun Qian},
title = {Embedded Deterministic Test for Low-Cost Manufacturing Test},
journal ={Test Conference, International},
volume = {0},
year = {2002},
isbn = {0-7803-7543-2},
pages = {301},
doi = {http://doi.ieeecomputersociety.org/10.1109/TEST.2002.1041773},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Test Conference, International
TI - Embedded Deterministic Test for Low-Cost Manufacturing Test
SN - 0-7803-7543-2
SP
EP
A1 - Januz Rajki,
A1 - Jerzy Tyzer,
A1 - Mark Kassab,
A1 - Nilanjan Mukherjee,
A1 - Rob Thompson,
A1 - Kun-Han Tsai,
A1 - Andre Hertwig,
A1 - Nagesh Tamarapalli,
A1 - Grzegorz Mrugalski,
A1 - Geir Eide,
A1 - Jun Qian,
PY - 2002
KW - null
VL - 0
JA - Test Conference, International
ER -
 
Januz Rajki, Mentor Graphics Corporation
Jerzy Tyzer, Poznan University of Technology
Mark Kassab, Mentor Graphics Corporation
Nilanjan Mukherjee, Mentor Graphics Corporation
Rob Thompson, Mentor Graphics Corporation
Kun-Han Tsai, Mentor Graphics Corporation
Andre Hertwig, Mentor Graphics Corporation
Nagesh Tamarapalli, Mentor Graphics Corporation
Grzegorz Mrugalski, Poznan University of Technology
Geir Eide, Mentor Graphics Corporation
Jun Qian, Cisco Systems
This paper introduces Embedded Deterministic Test (EDT) technology, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The EDT architecture, the compression algorithm, design flow, experimental results, and silicon implementation are presented.
Citation:
Januz Rajki, Jerzy Tyzer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian, "Embedded Deterministic Test for Low-Cost Manufacturing Test," itc, pp.301, International Test Conference 2002 (ITC'02), 2002
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