The Linear Error Mechanism Modeling Algorithm (LEMMA [1]) has been developed with the aim of reducing test costs for DACs and ADCs, a particularly important class of mixed-signal integrated circuits. In this contribution, for the example of a 12-bit ADC, we report on the development and verification of LEMMA in an industrial production test environment. From the insight gained, we estimate the requirements and return-of-investment for higher resolution devices where traditional test techniques exhaust the time budget allowed for testing commodity parts.