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Fault Injection for Verifying Testability at the VHDL Level
Charlotte, NC, USA September 30-October 02
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TEST.2003.1270833International Test Conference 2003 (I ...
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S. R. Seward, P. K. Lala, "Fault Injection for Verifying Testability at the VHDL Level," Test Conference, International, pp. 131, International Test Conference 2003 (ITC'03), 2003.
 
 
BibTex
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@article{ 10.1109/TEST.2003.1270833,
author = {S. R. Seward and P. K. Lala},
title = {Fault Injection for Verifying Testability at the VHDL Level},
journal ={Test Conference, International},
volume = {0},
year = {2003},
issn = {1089-3539},
pages = {131},
doi = {http://doi.ieeecomputersociety.org/10.1109/TEST.2003.1270833},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Test Conference, International
TI - Fault Injection for Verifying Testability at the VHDL Level
SN - 1089-3539
SP
EP
A1 - S. R. Seward,
A1 - P. K. Lala,
PY - 2003
KW - null
VL - 0
JA - Test Conference, International
ER -
 
S. R. Seward, University of Arkansas, Fayetteville
P. K. Lala, University of Arkansas, Fayetteville
This paper presents a technique to improve verification at the VHDL level of digital circuits by means of a specially designed fault injection block. The injection technique allows incorporation of both transient and permanent faults to varying levels of VHDL hierarchy, and helps in verifying the performance of a testable system.
Citation:
S. R. Seward, P. K. Lala, "Fault Injection for Verifying Testability at the VHDL Level," itc, pp.131, International Test Conference 2003 (ITC'03), 2003
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