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RIC/DICMOS-- Multi-channel CMOS Formatter
Charlotte, NC, USA September 30-October 02
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TEST.2003.1270838International Test Conference 2003 (I ...
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Ahmed Rashid Syed, "RIC/DICMOS-- Multi-channel CMOS Formatter," Test Conference, International, pp. 175, International Test Conference 2003 (ITC'03), 2003.
 
 
BibTex
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@article{ 10.1109/TEST.2003.1270838,
author = {Ahmed Rashid Syed},
title = {RIC/DICMOS-- Multi-channel CMOS Formatter},
journal ={Test Conference, International},
volume = {0},
year = {2003},
issn = {1089-3539},
pages = {175},
doi = {http://doi.ieeecomputersociety.org/10.1109/TEST.2003.1270838},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Test Conference, International
TI - RIC/DICMOS-- Multi-channel CMOS Formatter
SN - 1089-3539
SP
EP
A1 - Ahmed Rashid Syed,
PY - 2003
KW - null
VL - 0
JA - Test Conference, International
ER -
 
NPTest CMOS formatter, embedded within the new timing generation IC, can provide formatted levels and internal strobe markers for eight independent pin-electronics channels at up to 800 Mbps. The timing accuracy for both the formatted edges, and the strobe markers, is specified at +/- 81ps. The drive side minimum pulse-width is 1 ns, and the receive side can strobe pin-electronics comparator outputs as narrow as 800 ps. This paper describes the major features and operation of the new CMOS formatter.
Citation:
Ahmed Rashid Syed, "RIC/DICMOS-- Multi-channel CMOS Formatter," itc, pp.175, International Test Conference 2003 (ITC'03), 2003
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