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ASPEN: Towards Effective Simulation of Threads and Engines in Evolving Platforms
Volendam, The Netherlands October 04-October 08
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MASCOT.2004.134818112th IEEE International Symposium on ...
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Jaideep Moses, Intel Corporation
Ramesh Illikkal, Intel Corporation
Ravi Iyer, Intel Corporation
Ram Huggahalli, Intel Corporation
Don Newell, Intel Corporation
As platforms evolve from employing single-threaded, single-core CPUs to multi-threaded, multi-core CPUs and embedded hardware-assist engines, the simulation infrastructure required for performance analysis of these platforms becomes extremely complex. While investigating hardware/software solutions for Server Network Acceleration (SNA), we encountered limitations of existing simulators for some of these solutions. For example, Light Weight Threading and Asynchronous Memory Copy solutions for SNA could not be modeled accurately and efficiently and hence we developed a flexible trace-driven simulation framework called ASPEN. ASPEN is based on the use of rich workload traces (RWT), which capture the major events of interest during the execution of a workload on a single-threaded CPU and platform and replaying it a multi-threaded architecture with hardware-assist engines. We introduce the overall ASPEN framework and describe its usage in the context of SNA. We believe that ASPEN is a useful performance tool for future platform architects and performance analysts.
Citation:
Jaideep Moses, Ramesh Illikkal, Ravi Iyer, Ram Huggahalli, Don Newell, "ASPEN: Towards Effective Simulation of Threads and Engines in Evolving Platforms," mascots, pp.51-58, 12th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems (MASCOTS'04), 2004
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