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A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories
Isle of Bendor, France July 10-July 12
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MTDT.2002.1029766The 2002 IEEE International Workshop ...
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Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu, "A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 68, The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), 2002.
 
 
BibTex
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@article{ 10.1109/MTDT.2002.1029766,
author = {Rei-Fu Huang and Jin-Fu Li and Jen-Chieh Yeh and Cheng-Wen Wu},
title = {A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories},
journal ={Memory Technology, Design and Testin, IEEE International Workshop on},
volume = {0},
year = {2002},
issn = {1087-4852},
pages = {68},
doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2002.1029766},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Memory Technology, Design and Testin, IEEE International Workshop on
TI - A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories
SN - 1087-4852
SP
EP
A1 - Rei-Fu Huang,
A1 - Jin-Fu Li,
A1 - Jen-Chieh Yeh,
A1 - Cheng-Wen Wu,
PY - 2002
KW - embedded memory
KW - memory testing
KW - memory repair
KW - redundancy analysis
KW - simulation
VL - 0
JA - Memory Technology, Design and Testin, IEEE International Workshop on
ER -
 
Rei-Fu Huang, National Tsing Hua University
Jin-Fu Li, National Tsing Hua University
Jen-Chieh Yeh, National Tsing Hua University
Cheng-Wen Wu, National Tsing Hua University
We present a simulator for evaluating the redundancy analysis (RA) algorithms. The simulator can calculate the repair rate (the ratio of the number of repaired memories to the number of defective memories) of the given RA algorithm and the associated memory configuration and redundancy structure. With the tool, the user also can easily assess and plan the redundant (spare) elements, and subsequently develop the built-in redundancy analysis (BIRA) algorithms and circuits that are essential for built-in self-repair (BISR) of embedded memories. The simulator has another important feature — it can simulate the sequence of the detected faults in the real order, improving the accuracy of the analysis results.
Index Terms:
embedded memory, memory testing, memory repair, redundancy analysis, simulation
Citation:
Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu, "A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories," mtdt, pp.68, The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), 2002
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