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Adder Merged DRAM Architecture
Isle of Bendor, France July 10-July 12
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MTDT.2002.1029768The 2002 IEEE International Workshop ...
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Masashi Hashimoto, "Adder Merged DRAM Architecture," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 88, The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), 2002.
 
 
BibTex
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@article{ 10.1109/MTDT.2002.1029768,
author = {Masashi Hashimoto},
title = {Adder Merged DRAM Architecture},
journal ={Memory Technology, Design and Testin, IEEE International Workshop on},
volume = {0},
year = {2002},
issn = {1087-4852},
pages = {88},
doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2002.1029768},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Memory Technology, Design and Testin, IEEE International Workshop on
TI - Adder Merged DRAM Architecture
SN - 1087-4852
SP
EP
A1 - Masashi Hashimoto,
PY - 2002
KW - null
VL - 0
JA - Memory Technology, Design and Testin, IEEE International Workshop on
ER -
 
Masashi Hashimoto, Cadence Design Systems
A 4-level sensing scheme utilizing base-4 operation addition and subtraction executable DRAM array has been developed. Neither DRAM functions, performance, nor silicon area will be sacrificed by implementing the circuit. Addition/subtraction will be executed using the massively parallel SIMD, resulting in a high degree of concurrency. Performance of around 50GOPS performance can be achieved in the case where the adder is implemented into 64Mb DRAM array.
Citation:
Masashi Hashimoto, "Adder Merged DRAM Architecture," mtdt, pp.88, The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), 2002
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