Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC)

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http://doi.ieeecomputersociety.org/10.1109/MTDT.2002.1029778

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	T. Devoivre, M. Lunenborg, C. Julien, J-P. Carrere, P. Ferreira, W. J. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger, P. Vannier, Y. Trouiller, Y. Rody, P-J. Goirand, R. Palla, I. Thomas, F. Guyader, D. Roy, B. Borot, N. Planes, S. Naudet, F. Pico, D. Duca, F. Lalanne, D. Heslinga, M. Haond, "Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC)," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 157, The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), 2002.

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	@article{ 10.1109/MTDT.2002.1029778, author = {T. Devoivre and M. Lunenborg and C. Julien and J-P. Carrere and P. Ferreira and W. J. Toren and A. VandeGoor and P. Gayet and T. Berger and O. Hinsinger and P. Vannier and Y. Trouiller and Y. Rody and P-J. Goirand and R. Palla and I. Thomas and F. Guyader and D. Roy and B. Borot and N. Planes and S. Naudet and F. Pico and D. Duca and F. Lalanne and D. Heslinga and M. Haond}, title = {Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC)}, journal ={Memory Technology, Design and Testin, IEEE International Workshop on}, volume = {0}, year = {2002}, issn = {1087-4852}, pages = {157}, doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2002.1029778}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Memory Technology, Design and Testin, IEEE International Workshop on TI - Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC) SN - 1087-4852 SP EP A1 - T. Devoivre, A1 - M. Lunenborg, A1 - C. Julien, A1 - J-P. Carrere, A1 - P. Ferreira, A1 - W. J. Toren, A1 - A. VandeGoor, A1 - P. Gayet, A1 - T. Berger, A1 - O. Hinsinger, A1 - P. Vannier, A1 - Y. Trouiller, A1 - Y. Rody, A1 - P-J. Goirand, A1 - R. Palla, A1 - I. Thomas, A1 - F. Guyader, A1 - D. Roy, A1 - B. Borot, A1 - N. Planes, A1 - S. Naudet, A1 - F. Pico, A1 - D. Duca, A1 - F. Lalanne, A1 - D. Heslinga, A1 - M. Haond, PY - 2002 KW - null VL - 0 JA - Memory Technology, Design and Testin, IEEE International Workshop on ER -

T. Devoivre, STMicroelectronics

M. Lunenborg, PHILIPS Semiconductors

C. Julien, STMicroelectronics

J-P. Carrere, STMicroelectronics

P. Ferreira, STMicroelectronics

W. J. Toren, PHILIPS Semiconductors

A. VandeGoor, PHILIPS Semiconductors

P. Gayet, STMicroelectronics

T. Berger, STMicroelectronics

O. Hinsinger, STMicroelectronics

P. Vannier, STMicroelectronics

Y. Trouiller, LETI

Y. Rody, PHILIPS Semiconductors

P-J. Goirand, STMicroelectronics

R. Palla, STMicroelectronics

I. Thomas, STMicroelectronics

F. Guyader, STMicroelectronics

D. Roy, STMicroelectronics

B. Borot, STMicroelectronics

N. Planes, STMicroelectronics

S. Naudet, STMicroelectronics

F. Pico, STMicroelectronics

D. Duca, STMicroelectronics

F. Lalanne, STMicroelectronics

D. Heslinga, PHILIPS Semiconductors

M. Haond, STMicroelectronics

This paper presents a complete 90nm CMOS technology platform dedicated to advanced SoC manufacturing, featuring 16 Å EOT-70nm transistors (standard process) or 21 -90nm transistors (Low Power process) as well as 2.5 or 3.3V I/O transistors, copper interconnects and SiOC low-k IMD (k=2.9). The main critical process steps are described and electrical results are discussed. Moreover, using advanced lithographic tools, fully functional 1Mbit SRAM instances, based on a highly manufacturable 6T 1.36?m? memory cell, have been processed. The cell is detailed and its features, both electrical and morphological, are discussed.

Citation:

T. Devoivre, M. Lunenborg, C. Julien, J-P. Carrere, P. Ferreira, W. J. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger, P. Vannier, Y. Trouiller, Y. Rody, P-J. Goirand, R. Palla, I. Thomas, F. Guyader, D. Roy, B. Borot, N. Planes, S. Naudet, F. Pico, D. Duca, F. Lalanne, D. Heslinga, M. Haond, "Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC)," mtdt, pp.157, The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), 2002

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