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Converting an Embedded Low-Power SRAM from Bulk to PD-SOI
Isle of Bendor, France July 10-July 12
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MTDT.2002.1029780The 2002 IEEE International Workshop ...
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Mario R. Casu, Philippe Flatresse, "Converting an Embedded Low-Power SRAM from Bulk to PD-SOI," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 163, The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), 2002.
 
 
BibTex
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@article{ 10.1109/MTDT.2002.1029780,
author = {Mario R. Casu and Philippe Flatresse},
title = {Converting an Embedded Low-Power SRAM from Bulk to PD-SOI},
journal ={Memory Technology, Design and Testin, IEEE International Workshop on},
volume = {0},
year = {2002},
issn = {1087-4852},
pages = {163},
doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2002.1029780},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Memory Technology, Design and Testin, IEEE International Workshop on
TI - Converting an Embedded Low-Power SRAM from Bulk to PD-SOI
SN - 1087-4852
SP
EP
A1 - Mario R. Casu,
A1 - Philippe Flatresse,
PY - 2002
KW - null
VL - 0
JA - Memory Technology, Design and Testin, IEEE International Workshop on
ER -
 
Mario R. Casu, Politecnico di Torino
Philippe Flatresse, ST Microelectronics
The migration of an embedded 1 Mbit SRAM for low power applications from a 0.13\mu m Bulk to a Partially Depleted Silicon-on-Insulator (PDSOI) technology is described in this paper. Floating body effects such as threshold voltage variation and parasitic bipolar turn on and their impact on sense amplifiers, pass-gates based multiplexers and dynamic decoders are addressed. Solutions like the use of body contacts in specific parts are discussed. A SRAM chip with various testable configurations has been taped out.
Citation:
Mario R. Casu, Philippe Flatresse, "Converting an Embedded Low-Power SRAM from Bulk to PD-SOI," mtdt, pp.163, The 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), 2002
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