A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits

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http://doi.ieeecomputersociety.org/10.1109/MTV.2003.1250260

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	Jayanta Bhadra, Narayanan Krishnamurthy, Magdy Abadir, "A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits," Microprocessor Test and Verification, International Workshop on, pp. 32, Fourth International Workshop on Microprocessor Test and Verification Common Challenges and Solutions, 2003.

	BibTex	x
	@article{ 10.1109/MTV.2003.1250260, author = {Jayanta Bhadra and Narayanan Krishnamurthy and Magdy Abadir}, title = {A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits}, journal ={Microprocessor Test and Verification, International Workshop on}, volume = {0}, year = {2003}, isbn = {0-7695-2045-6}, pages = {32}, doi = {http://doi.ieeecomputersociety.org/10.1109/MTV.2003.1250260}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Microprocessor Test and Verification, International Workshop on TI - A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits SN - 0-7695-2045-6 SP EP A1 - Jayanta Bhadra, A1 - Narayanan Krishnamurthy, A1 - Magdy Abadir, PY - 2003 KW - null VL - 0 JA - Microprocessor Test and Verification, International Workshop on ER -

Jayanta Bhadra, Motorola Inc.

Narayanan Krishnamurthy, Motorola Inc.

Magdy Abadir, Motorola Inc.

In Motorola's High Performance Design Center, two verification flows are often used to verify correctness of custom designed blocks. The first is an equivalence checking flow, and the second is a manufacturing test pattern generation/simulation flow. The two flows are often disconnected resulting into silicon failures on manufacturing test vector suites. The goal in this paper is to analyze the disconnect and to arrive at a technique that bridges the gap between the two verification flows by validating the correctness of manufacturing test patterns. This reduces time to market by cutting down on precious silicon debug time by eliminating redundant defect fixes. Our experimental results were obtained from a set of custom designed circuits of a Motorola MPC74xx¹ microprocessor.

Citation:

Jayanta Bhadra, Narayanan Krishnamurthy, Magdy Abadir, "A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits," mtv, pp.32, Fourth International Workshop on Microprocessor Test and Verification Common Challenges and Solutions, 2003

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