Test model generation is crucial in the test generation process of a high-performance design. A key process in test model generation extracts a gate-level (logic) model from the transistor level representation of the circuit under test. Due to the limitation of the extraction tools and human interference, logic extraction may introduce errors. Such errors require a resource intensive and time consuming manual process to debug. This paper presents a set of extraction errors typical in an industrial environment. It also proposes an automated solution to extraction error diagnosis and correction. Experiments on circuits with architecture similar to high speed custom-made industrial blocks confirm the fitness of the approach.