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A New Memory Module for Memory Intensive Applications
Dresden, Germany September 07-September 10
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.5International Conference on Parallel ...
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Noboru Tanabe, Hironori Nakajo, Hirotaka Hakozaki, Masasige Nakatake, Yasunori Dohi, Hideharu Amano, "A New Memory Module for Memory Intensive Applications," Parallel Computing in Electrical Engineering, International Conference on, pp. 123-128, International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04), 2004.
 
 
BibTex
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@article{ 10.1109/PCEE.2004.5,
author = {Noboru Tanabe and Hironori Nakajo and Hirotaka Hakozaki and Masasige Nakatake and Yasunori Dohi and Hideharu Amano},
title = {A New Memory Module for Memory Intensive Applications},
journal ={Parallel Computing in Electrical Engineering, International Conference on},
volume = {0},
year = {2004},
isbn = {0-7695-2080-4},
pages = {123-128},
doi = {http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.5},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel Computing in Electrical Engineering, International Conference on
TI - A New Memory Module for Memory Intensive Applications
SN - 0-7695-2080-4
SP123
EP128
A1 - Noboru Tanabe,
A1 - Hironori Nakajo,
A1 - Hirotaka Hakozaki,
A1 - Masasige Nakatake,
A1 - Yasunori Dohi,
A1 - Hideharu Amano,
PY - 2004
KW - null
VL - 0
JA - Parallel Computing in Electrical Engineering, International Conference on
ER -
 
Noboru Tanabe, Toshiba
Hironori Nakajo, Tokyo University of Agriculture and Technology
Hirotaka Hakozaki, Yokohama National University
Masasige Nakatake, Yokohama National University
Yasunori Dohi, Yokohama National University
Hideharu Amano, Keio University
Some applications with gather / scatter operations are difficult to accelerate. These operations cause inefficient cache use in each processor and fine grain global communications in parallel systems. There are several applications with such characteristics particularly in electrical engineering. For examples, circuit simulation and power flow simulation with LU decomposition for random sparse matrix has such characteristics. This paper presents how to make inexpensive personal supercomputers to solve these problems. In order to get the merit of commercial-off-the-shelf (COTS) continuously after the death of vector supercomputer vendors, it is designed without any modification on CPU, bridge chips on motherboard and memory chips. Only plugging a new memory module with vector load / store function and communication functions make an inexpensive home-use personal computer into a node similar to Earth simulator's one. Applications with unit striding or indexed accesses are going to be accelerated. How to accelerate NAS CG is shown as an example.
Citation:
Noboru Tanabe, Hironori Nakajo, Hirotaka Hakozaki, Masasige Nakatake, Yasunori Dohi, Hideharu Amano, "A New Memory Module for Memory Intensive Applications," parelec, pp.123-128, International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04), 2004
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