loading...
Re-Configurable Parallel Stream Processor with Self-Assembling and Self-Restorable Micro-Architecture
Dresden, Germany September 07-September 10
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.60International Conference on Parallel ...
 This Article 
 
PDF
HTML
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Lev Kirischian, Ryerson University Toronto, Canada
Irina Terterian, Ryerson University Toronto, Canada
Pil Woo Chun, Ryerson University Toronto, Canada
Vadim Geurkov, Ryerson University Toronto, Canada
In this paper we present a concept of the self-assembling micro-architectures of Application Specific Virtual Processors for data-stream processing. The procedure for micro-architecture assembling is developed for Xilinx "Virtex" FPGA devices. It is shown that proposed approach allows a minimization of system resources for multi-task data-stream workload and gives ability for self-restoration of processing micro-architectures when hardware fault occurs. This Paper presents a description of system level architecture of run-time re-configurable multi-stream parallel processor for video applications and results gained on the prototype.
Citation:
Lev Kirischian, Irina Terterian, Pil Woo Chun, Vadim Geurkov, "Re-Configurable Parallel Stream Processor with Self-Assembling and Self-Restorable Micro-Architecture," parelec, pp.165-170, International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04), 2004
Usage of this product signifies your acceptance of the Terms of Use.