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Automatic Verification of Fault Tolerance Using Model Checking
Seoul, Korea December 17-December 19
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PRDC.2001.992685Eighth Pacific Rim International Symp ...
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Model checking is a technique that can make a verification for finite state systems absolutely automatic. We pro-pose a method for automatic verification of fault-tolerant systems using this technique. Unlike other related work, which is tailored to specific systems, we are aimed at providing a general approach to verification of fault tolerance. The main obstacle in model checking is state explosion. To avoid the problem, we design this method so that it can use SMV, a symbolic model checking tool. Symbolic model checking can overcome the problem by expressing the state space and the transition relation by Boolean functions. Assuming that a system to be verified is specified by guarded commands, we define a modeling language suited for describing guarded command programs and propose a translation method from the modeling language to the input language of SMV. We show the results of applying the proposed method to various examples to demonstrate the usefulness.
Citation:
Tomoyuki Yokogawa, Tatsuhiro Tsuchiya, Tsuchiya Kikuno, "Automatic Verification of Fault Tolerance Using Model Checking," prdc, pp.95, Eighth Pacific Rim International Symposium on Dependable Computing (PRDC'01), 2001
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