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Development of a Fail-Safe Microprocessor LSI with Self-Diagnosis Mechanism Depending on an M-Sequence Code Signature
Seoul, Korea December 17-December 19
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PRDC.2001.992697Eighth Pacific Rim International Symp ...
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A bus-level synchronized computer system is widely Utilized in the field of railway signaling of Japan. It may Be recognized that there is a problem of disadvantage in a manufacturing cost reduction. We intend to integrate a bus-level synchronized FS computer into an LSI chip in expectation of cost reduction and performance enhancement. An economical FS one-chip computer by utilizing system LSI technology is realized. It assures fail-safety by means of new fault diagnosis mechanism depending on an M-sequence code signature. In this paper, these contents and techniques are reported in detail.
Citation:
Sei Takahashi, Munehisa Taira, Hidetaka Saegusa, Takehiko Hoshino, Hideo Nakamura, "Development of a Fail-Safe Microprocessor LSI with Self-Diagnosis Mechanism Depending on an M-Sequence Code Signature," prdc, pp.191, Eighth Pacific Rim International Symposium on Dependable Computing (PRDC'01), 2001
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